Wissam Hassan Hlayhel

Associate professor
Computer Science - Statistics department - Section III - Tripoli
Speciality: Computer Science
Specific Speciality: Informatique
Interests: IT, Photography
Skills: Programming, Computer Architecture, Computer systems, DataBases, Enterprise Web Applications, Mobile Application, Modeling, Parallel Computing

Teaching 7 Taught Courses
(2014-2015) ILOG 516 - Web Applications : Architecture and Implementation

M2 Software Engineering

(2014-2015) ILOG 580 - Training

M2 Software Engineering

(2014-2015) Info 438 - Applications Mobile

M1 Computer Sciences

(2014-2015) Info 439 - Project

M1 Computer Sciences

(2014-2015) Info 203 - Imperative Programming I

BS Computer Sciences

(2014-2015) Info 319 - Web environment and XML

BS Computer Sciences

(2014-2015) Info 324 - Operating system II

BS Computer Sciences

Publications 4 publications
Jacques Henri Collet, Wissam Hlayhel, Daniel Litaize Parallel optical interconnects may reduce the communication bottleneck in symmetric multiprocessors Applied Optics, vol 40, 8 pages, Juillet 2001 2001

We start with a detailed analysis of the communication issues in today's symmetric multiprocessor (SMP) architectures to study the benefits of implementing optical interconnects (OI) in these machines. We show that the transmission of block addresses is the most critical communication bottleneck of future large SMPs owing to the need to preserve the coherence of data duplicated in caches. An address transmission bandwidth as high as 200-300 Gb/s may be necessary in ten years from now; this requirement will represent a difficult challenge for shared electric buses. In this context we suggest the introduction of simple point-to-point OIs for a SMP cache-coherent switch, i.e., for a VLSI switch that would emulate the shared-bus function. The operation might require as much as 10,000 input-outputs (IOs) to connect 100 processors, particularly if one maintains the present parallelism of transmissions to preserve a large bandwidth and a short memory access latency. The interest for OIs comes from the potential increase of the transmission frequency and from the possible integration of such a high density of IOs on top of electronic chips to overcome packaging issues. Then we consider the implementation of an optical bus that is a multipoint optical line involving more optical technology. This solution allows multiple simultaneous accesses to the bus, but the preservation of the coherence of caches can no longer be maintained with the usual fast snooping protocols.

Wissam Hlayhel, Jacques Collet, Daniel Litaize, Christine Rochange Pushing Away the Communication Bottleneck with Optical Bus-based Symmetric Multiprocessors SPIE 2000

We analyze the bandwidth needed for transmitting the addresses in future symmetric multiprocessor machines (SMP), constructed around a shared bus due to the critical obligation to preserve the coherence of the memory hierarchy. We show that an address-transaction bandwidth as high as several hundreds of Gbit/s will be necessary not to slow down the execution of most applications in large SMP's. This communication bandwidth seems incompatible with the operation constraints of shared electrical busses, making necessary the search for other implementations of the address transmission network. We consider the introduction of optical interconnects (OI) in this context. We review several solutions, in the ascending order of complexity of the optical subsystems as one critical issue concerns the degree of sophistication of the optical solutions and their cost. We first consider simple point to point OI's for a SMP chipset. The interest for OI's comes from the low energy consumption and from the possibility, in the future, to integrate several thousands of optical input/outputs per electronic chip. The we consider the implementation of an optical bus that is a multipoint optical line involving more optical functionality. We discuss the possibility of multiple accesses to the bus, and the constraints related to the necessity to maintain the coherence of caches

Wissam Hlayhel, Jacques Collet, Laurent Fesquet Implementing Snoop Coherence Protocol for Future SMP Architectures Springer LNCS - European Conference on Parallel Computing 1999

Maintaining the coherence is becoming one of the most serious problems faced when designing today’s machines. Initially, this problem was relatively simple when the interconnection network of Symmetric MultiProcessors (SMP) was an atomic bus, which simplified the implementation of invalidation coherence protocols. However, due to the increasing bandwidth demand, atomic busses have been progressively replaced by split busses that uncoupled the request and response phases of a transaction. Split busses enable initiating new requests before receiving the response to those already in progress but make more complicated the preservation of the coherence. Indeed, a new request induces a conflict when it concerns a block address involved by another current request and when one of the requests is aWRITE miss. Several solutions exist to solve this problem. That one used in the SGI machine is based on a shared data bus which traces the completion of transactions. Unfortunately, it becomes impracticable in the recent machines which replace data busses by more efficient networks (again for bandwidth constrains), ultimately by a crossbar. This work describes and quantitatively evaluates two possible solutions to the coherence problem for the new architectures where all the data responses cannot be traced by each processor.

Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Collet Optical versus Electronic Bus for Address-transactions in Future SMP Architectures IEEE Computer Society 1998

The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP) build around shared busses. This kind of multiprocessor is especially attractive because the problem of data coherency in caches can be solved by a class of snooping protocols specific to these shared-bus architecture. But the bandwidth demand, especially for the addresses, is becoming so important that a technological step must be considered. Optical communications are becoming mature, and bring a huge information bandwidth through the implementation of optical busses. This paper is focused on the address bandwidth needed by shared-bus SMP without suggesting a complete solution. We show that an optical address bus can fulfill the bandwidth demand of future SMPs contrarily to standard electronic busses


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